1. Field of the Invention
The invention relates to an operating method of a memory, and more particularly, to a programming method of a memory array.
2. Description of Related Art
A flash memory can adopt a memory array having a NAND architecture. In particular, a NAND memory array includes a plurality of memory cell strings, and the storage state of the memory cells in the memory cell strings can be changed through a programming operation. In terms of the programming of the memory array, the state of the memory cell strings can be switched to a inhibit state or a selected state to stop or perform the programming of the memory cells in the memory cell strings. Moreover, the programming of the memory array can adopt an incremental step pulse program (ISPP) method to repeatedly apply a programming voltage to the memory cells and to increase the level of the programming voltage in every cycle operation.
However, as the size of the memory cells is reduced, programming of the memory array adopting an ISPP method is often very readily affected by parasitic capacitors. For instance, during the programming process of the memory array, each of the memory cell strings respectively forms a channel, and parasitic capacitor may be generated between a floating gate of a memory cell and a channel of an adjacent memory cell string thereof. Moreover, when the states of two adjacent memory cell strings are different, the parasitic capacitor between the floating gate of the memory cell and an adjacent channel thereof causes the distribution of the threshold voltage corresponding to the storage state of the memory cell to increase, such that the programming method of the memory array adopting an ISPP method often cannot meet the application of a multi-level cell (MLC). Therefore, how to avoid the influence to the programming of the memory array caused by the parasitic capacitor between the floating gate of the memory cells and an adjacent channel thereof is a current and important topic to be solved by industries.